Architectural Support for an Efficient Implementation of a Software-Only Directory Cache Coherence Protocol

Software-only directory cache coherence protocols emulate directory management by handlers executed on the compute processor in shared-memory multiprocessors. While their potential lies in lower implementation cost and complexity than traditional hardware-only directory protocols, the miss penalty for cache misses induced by application data accesses as well as directory accesses is a critical issue to address. In this paper, we study important support mechanisms for software-only directory protocols in the context of a processor node organization for a cache-coherent NUMA architecture. We find that it is possible to remove or hide software handler latency for local as well as remote read misses by adopting simple hardware support mechanisms. To further reduce the overhead of software handler execution, we study the effects of directory data caching. While this could pollute the caches, our results suggest that this effect is marginal and that software handler execution overhead is drastically reduced by allowing caching. Overall, the softwareonly directory protocol enhanced with the miss handling support mechanisms exhibits a performance that is competitive with hardware-only protocols but with a lower cost and complexity.